1. Field of the Invention
The present invention relates to circuits for protecting integrated circuit devices from electrostatic discharges, and more specifically to protection circuits of compact size for mixed technology integrated circuit devices that operate with low supply voltages.
2. Description of Related Art
The contact pads of an integrated circuit device can inadvertently come into contact with electrically charged objects during fabrication, assembly to a host circuit, or operation. Such contact can create electric potential differences between different areas of the integrated circuit that are of sufficient magnitude to damage or even destroy thin dielectrics (e.g., gate oxides of MOS transistors) in the device. In other words, if the potential difference caused by electrostatic discharges (ESDs) exceeds the dielectric strength of the gate insulation, there will be a break down of the gate insulation and the associated MOS transistor will become unusable. For example, such destructive effects can occur in a CMOS integrated circuit device with a minimum gate size of 1.2 .mu.m at voltages in the 12V range, which is much lower than the voltages that can be produced by ESDs. Further, avalanche reverse conduction phenomena can set in and cause the junctions to break down.
There are various conventional ways for protecting the input and output terminals of an integrated circuit device against electrostatic discharges. For example, some circuits typically used to protect input terminals employ resistors in series or diodes in series or in parallel that are integrated to the substrate of the integrated circuit itself in order to limit the currents caused by ESDs. More complex circuits for protecting input or output terminals from ESDs utilize a thyristor structure or siliconcontrolled rectifiers (SCRs) with modifications to lower the triggering voltage of the device.
FIG. 1 shows an input protection circuit for a BiCMOS type device (i.e., a mixed technology integrated circuit device). Two transistors Q1 and Q2 are arranged so as to form a structure that is equivalent to a Zener diode connected between the input terminal IN and ground GND. Such an ESD protection circuit and its operation are described in the book "BiCMOS Technology and Applications," Second Edition, by A. R. Alvarez, Cypress Semiconductor Corporation of San Jose, California. The circuit of FIG. 1 provides a highly compact protection circuit that can readily be integrated in a BiCMOS type process and that is quite effective in integrated circuit devices having a protection circuit for each ESD sensitive terminal.
However, for devices integrated using mixed-type (e.g., BiCMOS) processes in which an epitaxial layer is grown on the surface of a monocrystalline silicon substrate, ESD protection circuits can interfere with proper circuit operation if the epitaxial wells of the protectors are directly connected to the protected terminals. In particular, during an electrostatic discharge, the directly connected epitaxial wells can act as parasitic collectors for substrate currents (i.e., a parasitic NPN transistor is activated in the event of a ground loop) so as to cause a latch-up, which is a regenerative phenomenon with destructive consequences that is caused by parasitic bipolar structures of the SCR type. Additionally, the parasitic well capacitance can produce an antenna effect and switching type disturbance that alters the functionality of the circuit coupled to the protected terminal.